I was born December, 22, 1979. In 1997 I entered in
Donetsk national technical university on faculty of computer
science and computer facilities. During studing I has mastered programming
languages Assembler, Pascal, C ++, Java Script, Java, Perl, and also language
of the description of hardware VHDL, I has seized following tool means Borland
With ++ Builder, Borland Java Builder, Borland Delphi etc. In May, 2001 I
took part in the testing spent to Kiev
by American company Aldec Inc. By its results
I received certificates in nominations VHDL Behavorial and VHDL Synthesis.
In the summer of the same year I had an industrial training in Krakow
(Poland) in the Polish division of company Aldec. During the training I seized
tool means Aldec Active-HDL, Aldec Design Verification Manager, Xilinx Foundation,
Mentor ModelSim, Synopsys FPGA Express, Synopsys FPGA Compiler, Sinplicity
Sinplify etc., has familiarized with HES-technology (Hardware Embeded Simulation)
developed by Alatek Inc, operational system
SunOS, local sights and water
park.
In 2001 I received the bachelor's degree in specialities "Computer systems
and networks" and economist-bookkeeper. A theme of magistracy work is
" Development algorithm of testing of FPGA-devices " (Field Programmable
Gate Array).
Examples of works are available at russian page only.